Preface
Acknowledgements

1. Architecture and Machines
2. Time, Area, and Instruction Sets
3. Data: How Programs Behave
4. Pipelined Processor Design
5. Cache Memory
6. Memory System Design
7. Concurrent Processors
8. Shared Memory Multiprocessors
9. I/O and the Storage Hierarchy
10. Processor Studies

Appendices:
A. DTMR Cache Miss Rates
B. SPECmark vs.. DTMR Cache Performance
C. Modeling System Effects in Caches
D. New DRAM Technologies
E. M/G/1 Queues
F. Some Details on Bus-Based Protocols
Bibliography
Index